___________allows DMA controller to transfer one data word at time after which it must return control of the buses to the CPU.*CISCDMA Cycle stealDMA BurstRISC
Question
___________ allows DMA controller to transfer one data word at time after which it must return control of the buses to the CPU.
- CISC
- DMA Cycle steal
- DMA Burst
- RISC
Solution
The correct answer to the question is DMA Cycle steal.
Explanation
The term "cycle steal" refers to a mode of operation for the Direct Memory Access (DMA) controller, where the DMA transfers one data word at a time. After each transfer, the control of the buses is returned to the CPU, allowing the CPU to perform other tasks in between DMA transfers. This method helps in balancing the performance needs of both the CPU and the DMA, ensuring that the CPU is not idle for extended periods while data is being transferred.
In contrast, DMA burst mode would allow the DMA to take control of the buses for multiple data words in one go without returning control to the CPU until the burst is complete. Thus, "cycle steal" is the most accurate term for the given definition.
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