In which one of the following combinations of both SDA and SCL signals are high in the I2C protocol?

In the I2C (Inter-Integrated Circuit) protocol, both the SDA (Serial Data Line) and SCL (Serial Clock Line) signals are high during the idle or bus free condition. This is a standard condition when no device is transmitting any data.

Here are the steps to understand this:

1. I2C protocol is a synchronous, multi-master, multi-slave, packet switched, single-ended, serial communication bus invented by Philips Semiconductor (now NXP Semiconductors).

2. It is widely used for attaching lower-speed peripheral ICs to processors and microcontrollers in short-distance, intra-board communication.

3. The I2C bus uses two wires: serial data (SDA) and serial clock (SCL). All I2C master and slave devices are connected with only those two wires. Each device can be a transmitter, a receiver or both.

4. The bus has two states: idle and active. When the bus is idle, both lines (SDA and SCL) are high.

5. When data is being transmitted, these lines can change states. The SDA line changes state while the SCL line is high during the start and stop conditions. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as control signals.

So, in conclusion, both SDA and SCL signals are high in the I2C protocol when the bus is idle.