The last stage of a 5-stage SimpleRISC processor is the ____. Instruction Fetch (IF) Operand Fetch (OF) Register Write (RW) Memory Access (MA)

The last stage of a 5-stage SimpleRISC processor is the Register Write (RW) stage.

In a typical 5-stage pipeline architecture like SimpleRISC, the stages consist of:

1. Instruction Fetch (IF): The processor fetches the instruction from memory.
2. Operand Fetch (OF): The processor reads the operands from the registers.
3. Execution (EX): The processor executes the instruction (not explicitly listed in your question but typically included).
4. Memory Access (MA): The processor accesses memory if required (for load or store operations).
5. Register Write (RW): The final stage where the result of the executed instruction is written back to the register file.

Thus, Register Write is the correct answer for the last stage in this sequence.